Exemplary embodiments relate to a semiconductor integrated circuit. More particularly, exemplary embodiments relate to a semiconductor integrated circuit which reduces power consumption by having a new clock path for transmission of a clock signal, and a method of operating the same.
With the spread of portable devices, such as smart phones and tablet personal computers (PCs), and the increase of applications available in the portable devices, approaches for reducing power consumption of the portable devices is needed. The portable devices of the related art may include many synchronization circuits which operate in synchronization with a clock signal. As an example of the related art, dynamic voltage and frequency scaling (DVFS) is a method for reducing power consumed by synchronization circuits. DVFS is a power-saving technique used in various types of synchronization circuits.
DVFS is a related art technique that increases the voltage and frequency of a portable device when the portable device shows the maximum performance. Further, DVFS in the related art decreases the frequency according to necessary performance for an application of the portable device, and decreases the voltage to a level that can be driven at the decreased frequency, when the maximum performance is not needed. Thus, the power consumption of the portable device in the related art is reduced. According to DVFS in the related art, decreasing the voltage exerts more influence on the reduction of power consumption than decreasing the frequency. However, semiconductor integrated circuits are designed to satisfy maximum performance. As a result, when the portable device of the related art does not require the maximum performance, a clock network for high-end products designed for the maximum performance will require greater power consumption than the performance needs.